// div50to2p048_tb
// 50M分频2.048M_tb

module div50to2p048_tb ();
    
    reg clk_50,rst_n;
    wire clk_2p048;
    
    div50to2p048 tb (
        .clk_50(clk_50),
        .rst_n(rst_n),
        .clk_2p048(clk_2p048)
    );

    initial begin
        clk_50  = 0;
        rst_n     = 1;
        #20 rst_n = 0;
        #20 rst_n = 1;
        
        
        #5000 $stop;
    end

    always  begin
        #5 clk_50 = ~clk_50;
    end
    
endmodule
